Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Methods and apparatus for testing delay locked loops and clock skew

Methods and apparatus for testing delay locked loops and clock skew

US Patent 7355380 · Granted Apr 8, 2008

Estimated economic value: $1,403,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Clock gating for scan shift clock in a mesh clock environment2025
System and method for performing a failure assessment of an integrated circuit2023
Measuring delay between signal edges of different signals using an undersampling2016
Methods and apparatus for testing delay locked loops and clock skew2010
Methods and apparatus for testing delay locked loops and clock skew2010
Massively parallel computer including auxiliary vector processor2001
Massively parallel computer including auxiliary vector processor1999
Digital clock buffer circuit providing controllable delay1992