Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › VLSI architecture and implementation for single cycle insertion of multiple records into a priority sorted list

VLSI architecture and implementation for single cycle insertion of multiple records into a priority sorted list

US Patent 7281009 · Granted Oct 9, 2007

Estimated economic value: $13,141,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Method and apparatus for data rate controller for a code block multiplexing sche2017
Method and apparatus for data rate controller for a code block multiplexing sche2014
Apparatus and method for a dual mode standard and layered belief propagation LDP2014