Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › System for reducing power consumption in a microprocessor having multiple instruction decoders that are coupled to selectors receiving their own output as feedback

System for reducing power consumption in a microprocessor having multiple instruction decoders that are coupled to selectors receiving their own output as feedback

US Patent 7263621 · Granted Aug 28, 2007

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Fast response circuits and methods for FRAM power loss protection2013
Systems and method for improved data retrieval from memory on behalf of bus mast2009
System, method, and apparatus for reducing power consumption in a microprocessor2007
Apparatus and method for assuming mastership of a bus2006
Synchronizer apparatus for synchronizing data from one clock domain to another c2006
Gate oxide protection method2002
Programmable high speed quiet I/O cell2001
Voltage translator with gate oxide breakdown protection2000
Gate oxide breakdown protection circuit for deep submicron processes2000
Clock system with internal monitor circuitry for secure testing1997
Circuit for connecting a node to a voltage source selected from alternative volt1996
Overvoltage protection1996