Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method and metric for low power standard cell logic synthesis

Method and metric for low power standard cell logic synthesis

US Patent 7260808 · Granted Aug 21, 2007

Estimated economic value: $9,988,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Method of stitching scan flipflops together to form a scan chain with a reduced 2011
ESD structure that protects against power-on and power-off ESD event2011
High voltage CMOS output buffer constructed from low voltage CMOS transistors2011
Floating diodes2010
PECL/LVPECL input buffer that employs positive feedback to provide input hystere2009
Wideband power-on reset circuit2009
High speed, low power, pipelined zero crossing detector that utilizes carry save2008
Wideband power-on reset circuit with glitch-free output2008
Flipflop that can tolerate arbitrarily slow clock edges2007
High speed, universal polarity full adder which consumes minimal power and minim2007
Low power, high speed logic controller that implements thermometer-type control 2006
High speed synchronizer for simultaneously initializing rising edge triggered an2006