Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method and/or apparatus for performing static timing analysis on a chip in scan mode with multiple scan clocks

Method and/or apparatus for performing static timing analysis on a chip in scan mode with multiple scan clocks

US Patent 7231567 · Granted Jun 12, 2007

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Centralized recording and processing of received packet parameters2014
Canonical signed digit (CSD) coefficient multiplier with optimization2010
Circuit and method for patching for program ROM2010
Processing multiplex sublayer data unit data in hardware2009
Waveform generation for FM synthesis2008
Method and/or architecture implemented in hardware for the adjustment of message2008
Method and/or apparatus implemented in hardware to discard bad logical transmiss2008
Read enable generator for a turbo decoder deinterleaved symbol memory2007
Flow control for interfaces providing retransmission2007
Method and system for a lock detector for a phase-locked loop2007
Method and/or apparatus for generating a write gated clock signal2006
Method and/or apparatus for generating a write gated clock signal2006