Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Low stress flip-chip package for low-K silicon technology

Low stress flip-chip package for low-K silicon technology

US Patent 7190082 · Granted Mar 13, 2007

Estimated economic value: $3,947,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

System packaging for cellular modem and transceiver system of heterogeneous stac2025
Molded silicon on passive package2024
Regulator circuit package techniques2024
Three-dimensional packaging techniques for power FET density improvement2022
Electronic module for high power applications2022
Package with overhang inductor2022
Regulator circuit package techniques2021
Structure and method for hybrid optical package with glass top cover2019
Optical sensor having a light emitter and a photodetector assembly directly moun2017
Embedded die redistribution layers for active device2016
Sacrificial pad on semiconductor package device and method2016
Wafer level lens in package2016