Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Semiconductor device with MOS transistors with an etch-stop layer having an improved residual stress level and method for fabricating such a semiconductor device

Semiconductor device with MOS transistors with an etch-stop layer having an improved residual stress level and method for fabricating such a semiconductor device

US Patent 7187038 · Granted Mar 6, 2007

Estimated economic value: $5,725,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Template for growing a crystal of a two-dimensional material2025
Chip containing an onboard non-volatile memory comprising a phase-change materia2025
Strained-channel fin FETs2025
Method to induce strain in finFET channels from an adjacent region2025
Method to induce strain in FINFET channels from an adjacent region2024
Gate spacer patterning2023
Transistor comprising a channel placed under shear strain and fabrication proces2023
Chip containing an onboard non-volatile memory comprising a phase-change materia2023
Method to induce strain in finFET channels from an adjacent region2023
Method to induce strain in 3-D microfabricated structures2023
Semiconductor device with fin and related methods2022
Co-integration of tensile silicon and compressive silicon germanium2022