Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Delay equalized Z/2Z ladder for digital to analog conversion

Delay equalized Z/2Z ladder for digital to analog conversion

US Patent 7132970 · Granted Nov 7, 2006

Estimated economic value: $10,947,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Voltage supply for supplying in zones voltages proportional to a master supply v2016
Full-duplex driver with hybrid adaptation2016
Distributed virtual-ground switching for SAR and pipelined ADC2016
Pipelined interpolating sub-ranging SAR analog-to-digital converter2016
Rail-to-rail line driver using differential cascode bootstraping2016
Power efficient driver architecture2016
System and method for power control in a physical layer device2016
Class AB differential line drivers2015
Current-mode line driver2014
Cabinet assembly2011
Digital calibration loop for an analog to digital converter2009
System for shifting data bits multiple times per clock cycle2009