Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Reducing memory access latencies from a bus using pre-fetching and caching

Reducing memory access latencies from a bus using pre-fetching and caching

US Patent 7089367 · Granted Aug 8, 2006

Estimated economic value: $12,359,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Graphics processing unit processing and caching improvements2025
Unified stateless compression system for universally consumable compression2025
Coordination and increased utilization of graphics processors during inference2025
Regional adjustment of render rate2025
Neural network optimization mechanism2025
System, apparatus and method for increasing performance in a processor during a 2025
Engine to enable high speed context switching via on-die storage2025
System-on-a-chip (SoC) architecture for low power state communication2025
Dynamic memory reconfiguration2025
Atomic handling for disaggregated 3D structured SoCs2025
Compute optimizations for low precision machine learning operations2025
Prefetch status notification for memory prefetching2025