Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Double data rate synchronous SRAM with 100% bus utilization

Double data rate synchronous SRAM with 100% bus utilization

US Patent 7069406 · Granted Jun 27, 2006

Estimated economic value: $6,140,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Method and apparatus for fast PLL initialization2012
Method and apparatus for ground bounce and power supply bounce detection2011
Method and apparatus for adjusting PLL and/or DLL timing offsets2011
Method and apparatus for cross-point detection2010
Method and apparatus for ground bounce and power supply bounce detection2009
Random access memory architecture and serial interface with continuous packet ha2006
Quad data rate RAM2002