Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Array architecture and operating methods for digital multilevel nonvolatile memory integrated circuit system

Array architecture and operating methods for digital multilevel nonvolatile memory integrated circuit system

US Patent 7035151 · Granted Apr 25, 2006

Estimated economic value: $5,696,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Adaptive bias decoder for non-volatile memory system2025
Adaptive bias decoder for non-volatile memory system2025
Current-to-voltage converter comprising common mode circuit2025
Output block for array of non-volatile memory cells2025
Row decoder and row address scheme in a memory system2025
Split array architecture for analog neural memory in a deep learning artificial 2025
Output array neuron conversion and calibration for analog neural memory in deep 2025
Neural network classifier using array of three-gate non-volatile memory cells2025
Memory device of non-volatile memory cells2025
Analog neural memory array in artificial neural network with source line pulldow2025
Deep learning neural network classifier using non-volatile memory array2025
Neural network classifier using array of three-gate non-volatile memory cells2025