Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Linear associative memory-based hardware architecture for fault tolerant ASIC/FPGA work-around

Linear associative memory-based hardware architecture for fault tolerant ASIC/FPGA work-around

US Patent 6999952 · Granted Feb 14, 2006

Estimated economic value: $45,222,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Multipurpose cutting tool2025
Linear associative memory-based hardware architecture for fault tolerant ASIC/FP2010
Source code debugging method and apparatus for use in script testing environment2010
Memory leak detection system and method using contingency analysis2007