Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Apparatus for reducing the overhead of cache coherency processing on each primary controller and increasing the overall throughput of the system

Apparatus for reducing the overhead of cache coherency processing on each primary controller and increasing the overall throughput of the system

US Patent 6983396 · Granted Jan 3, 2006

Estimated economic value: $6,490,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Fault-tolerant memory appliance2025
Intelligent management of ferroelectric memory in a data storage device2025
Balancing power, endurance and latency in a ferroelectric memory2025
System on chip (SOC) with processor and integrated ferroelectric memory2024
Read destructive memory wear leveling system2024
Non-volatile memory cell with multiple ferroelectric memory elements (FMEs)2024
Stack register having different ferroelectric memory element constructions2024
Front end buffer having ferroelectric field effect transistor (FeFET) based memo2024
Intelligent cache with read destructive memory cells2024
Data storage with multi-level read destructive memory2024
Intelligent management of ferroelectric memory in a data storage device2023
Data storage system with write back cache2023