Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Circuit arrangement and method for reducing an alignment error in a Σ-Δ modulator

Circuit arrangement and method for reducing an alignment error in a Σ-Δ modulator

US Patent 6927718 · Granted Aug 9, 2005

Estimated economic value: $62,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Bone fixation member systems and methods of use2017
Caps for implants, implant assemblies, and methods of use2016
Emulation of analog-to-digital converter characteristics2011
Firearm sight having two parallel video cameras2010
Digital amplifier with analogue error correction circuit2010
Sigma-delta modulator having a clocked delay line2007
Apparatus for the manufacture of compacts2003
Artificial hip joint socket2002
Device for the manufacture of tablets1999
Current mirror1997
Switched capacitor network1996
Switched capacitor network1996