Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Arrangement for testing a network device by interfacing a low speed emulation system with high speed CPU

Arrangement for testing a network device by interfacing a low speed emulation system with high speed CPU

US Patent 6892174 · Granted May 10, 2005

Estimated economic value: $7,763,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Maintaining synchronization between frame control word and data frame pairs in a2006
Arrangement for verifying that memory external to a network switch and the memor2006
Home network transmission deferral2005
Arrangement for verifying randomness of TBEB algorithm in a media access control2005
Verification of collision detection and resolution in a home network2005
Performing a two-step read on a MAC register in a home network as an atomic read2004
Arrangement for testing pause frame response in a network switch2004
Arrangement for reducing a media independent interface speed in a network switch2004
Arrangement for testing light emitting diode interface of an integrated network 2003