Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method for erasing a memory sector in virtual ground architecture with reduced leakage current

Method for erasing a memory sector in virtual ground architecture with reduced leakage current

US Patent 6819591 · Granted Nov 16, 2004

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Apparatuses and methods for signal encryption in high bandwidth memory2025
Adaptive write scheme for memory devices2025
Flexible and configurable bit error rate reduction for non-volatile memory2025
System and method for SEU detection and correction2025
ECC optimization2025
Single port memory with multiple memory operations per clock cycle2025
Cascaded reference based thin-oxide only N-well steering circuit for contention 2024
Single event upset tolerant memory device2024
Work machine2024
Apparatuses and methods for signal encryption in high bandwidth memory2023
Reference less glitch detection circuitry with autocalibration2023
In-memory computing apparatus and computing method having a memory array include2023