Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Fuse configuration with modified capacitor border layout for a semiconductor storage device

Fuse configuration with modified capacitor border layout for a semiconductor storage device

US Patent 6803301 · Granted Oct 12, 2004

Estimated economic value: $96,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Heat treatable coated article having antireflective coating(s) on substrate2025
Silver colored coated article with low-E coating having absorber layer and low v2021
Grey colored coated article with low-E coating having absorber layer and low vis2021
Heat treatable coated article with carbon-doped zirconium based layer(s) in coat2020
Heat sink assembly2019
Illuminated nock assembly2013
System and method for storing parity information in fuses2004
Process for forming a semiconductor device including a capacitor1998
Chamber for the treatment of cells in an electrical field1988
Apparatus for measuring the pressure in a very small volume1980