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Home › Method of forming double-gated silicon-on-insulator (SOI) transistors with reduced gate to source-drain overlap capacitance

Method of forming double-gated silicon-on-insulator (SOI) transistors with reduced gate to source-drain overlap capacitance

US Patent 6787404 · Granted Sep 7, 2004

Estimated economic value: $231,000 ⓘ

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