Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Programmable logic device verification system and method

Programmable logic device verification system and method

US Patent 6772381 · Granted Aug 3, 2004

Estimated economic value: $1,898,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Dynamic pulse width programming of programmable logic devices2003
Dynamic pulse width programming of programmable logic devices2003