Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Semiconductor structure having elevated salicided source/drain regions and metal gate electrode on nitride/oxide dielectric

Semiconductor structure having elevated salicided source/drain regions and metal gate electrode on nitride/oxide dielectric

US Patent 6674135 · Granted Jan 6, 2004

Estimated economic value: $4,179,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

3D horizontal memory cell with sequential 3D vertical stacking2025
3D multiple location compressing bonded arm for advanced integration2025
2D material to integrate 3D horizontal nanosheets using a carrier nanosheet2025
Methods for forming high performance three dimensionally stacked transistors bas2025
Epitaxial semiconductor 3D horizontal nano sheet with high mobility 2D material 2025
3D device with a plurality of core wiring layout architecture2025
Plurality of devices in adjacent 3D stacks in different circuit locations2025
High performance new channel materials precision aligned 3D CFET device architec2025
3D isolation of a segmentated 3D nanosheet channel region2025
Semiconductor devices and methods of manufacturing thereof2025
3D memory with cell stacking using an in-situ capacitor stack2025
3D semiconductor device with 2D semiconductor material and method of forming the2025