{"@context": "https://schema.org", "@type": "BreadcrumbList", "itemListElement": [{"@type": "ListItem", "position": 1, "name": "Home", "item": "https://www.patentleaderboard.com/"}, {"@type": "ListItem", "position": 2, "name": "Phase-locked loop (PLL) circuit for selectively correcting clock skew in different modes", "item": "https://www.patentleaderboard.com/patent/6647081"}]}
Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025

Phase-locked loop (PLL) circuit for selectively correcting clock skew in different modes

US Patent 6647081 · Granted Nov 11, 2003

Estimated economic value: $29,260,000

Assignee

Inventors

View full patent text on Google Patents →