Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method and system for efficient cache memory updating with a least recently used (LRU) protocol

Method and system for efficient cache memory updating with a least recently used (LRU) protocol

US Patent 6643742 · Granted Nov 4, 2003

Estimated economic value: $42,713,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Integrating intellectual property (IP) blocks into a processor2015
Technique for synchronizing faults in a processor having a replay system2007
Technique for synchronizing faults in a processor having a replay system2003
Method and apparatus for generating event handler vectors based on both operatin1999
Having write merge and data override capability for a superscalar processing dev1998
Multi-port register1998
Method and apparatus for disabling interrupts in a highly pipelined processor1998
Instruction pointer limits in processor that performs speculative out-of-order i1998
Method and apparatus for handling code segment violations in a computer system1998
Superscalar processor with a multi-port reorder buffer1996
Methods and apparatus for determining the next instruction pointer in an out-of-1995