Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method and circuit configuration for a memory for reducing parasitic coupling capacitances

Method and circuit configuration for a memory for reducing parasitic coupling capacitances

US Patent 6639846 · Granted Oct 28, 2003

Estimated economic value: $154,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Array of synchronized memory modules2006
Circuit configuration for receiving at least two digital signals2005
Test circuit for testing a digital semiconductor circuit configuration2001
Test circuit and testing method for function testing of electronic circuits2000
Integrated semiconductor circuit1998
Semiconductor component with protective structure for protecting against electro1997
Pulse enhancement circuit for digital integrated circuit1985