Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Integrated semiconductor memory configuration with a buried plate electrode and method for its fabrication

Integrated semiconductor memory configuration with a buried plate electrode and method for its fabrication

US Patent 6627934 · Granted Sep 30, 2003

Estimated economic value: $187,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Layer arrangement2008
Microelectronic structure having a hydrogen barrier layer2007
Method and apparatus for storing and reading information in a ferroelectric mate2007
Monolithic integrated circuit arrangement2007
Strip conductor arrangement and method for producing a strip conductor arrangeme2006
Contact-making structure for a ferroelectric storage capacitor and method for fa2005
Method of manufacturing a ferroelectric capacitor configuration2005
Storage capacitor and associated contact-making structure and a method for fabri2005
Method for removing structures2004
Method of patterning ferroelectric layers2004
Monitoring system for a conveying device for flat articles, especially wafers2004
Method for fabricating non-volatile memories2003