Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › System and method for parallel testing of IEEE 1149.1 compliant integrated circuits

System and method for parallel testing of IEEE 1149.1 compliant integrated circuits

US Patent 6618827 · Granted Sep 9, 2003

Estimated economic value: $12,720,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

System and method to qualify data capture2010
System and method for data analysis2010
System and method for generating a trigger signal2008
System and method to control data capture2007
Method and system for sensing IC package orientation in sockets2004
Method and system for sensing the status of a ZIF socket lever2004
System and method for testing an interface between two digital integrated circui2003