Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Layout technique for semiconductor processing using stitching

Layout technique for semiconductor processing using stitching

US Patent 6605488 · Granted Aug 12, 2003

Estimated economic value: $4,533,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Active pixel sensor with reduced fixed pattern noise2011
Semiconductor imaging sensor array devices with dual-port digital readout2010
Active pixel sensor (APS) readout structure with amplification2009
Active pixel sensor with reduced fixed pattern noise using two active regions2009
CMOS imager decoder structure2007
Embroidery of patterns2006
Semiconductor imaging sensor array devices with dual-port digital readout2005
Active pixel sensor with reduced fixed pattern noise2005
Active pixel sensor (APS) readout structure with amplification2005
Compressing information using CAM for narrow bit pattern output2004
Stitched circuits larger than the maximum reticle size in sub-micron process2004
Multi-chip addressing for the I2C bus2003