Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Single-edge clock adjustment circuits for PLL-compatible, dynamic duty-cycle correction circuits

Single-edge clock adjustment circuits for PLL-compatible, dynamic duty-cycle correction circuits

US Patent 6583657 · Granted Jun 24, 2003

Estimated economic value: $21,997,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Hemostatic pad assembly kit and method2022
Hemostatic pad assembly kit and method2020
Multi-output PLL output shift2012
Multi-output PLL output shift2012
Chip design and fabrication method optimized for profit2011
Digital circuit to measure and/or correct duty cycles2011
Integrated circuit chip having on-chip signal integrity and noise verification u2010
Efficient electromagnetic modeling of irregular metal planes2010
Electromagnetic morphing apparatus for hot pluggable architected systems2010
Method for controlling operation of microprocessor which performs duty cycle cor2010
Phase lock loop jitter measurement2010
Compact chip package macromodels for chip-package simulation2009