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Home › METHOD AND CIRCUIT FOR INCLUDING PARITY BITS IN WRITE DATA OF A MASS DATA STORAGE DEVICE, OR THE LIKE, USING A 48/54 MTR (3:K) CODE CONSTRAINT, AND POST-PROCESSING CIRCUIT AND METHOD FOR PROCESSING READ BACK DATA THAT INCLUDES SAID CODE CONSTRAINT

METHOD AND CIRCUIT FOR INCLUDING PARITY BITS IN WRITE DATA OF A MASS DATA STORAGE DEVICE, OR THE LIKE, USING A 48/54 MTR (3:K) CODE CONSTRAINT, AND POST-PROCESSING CIRCUIT AND METHOD FOR PROCESSING READ BACK DATA THAT INCLUDES SAID CODE CONSTRAINT

US Patent 6581184 · Granted Jun 17, 2003

Estimated economic value: $27,017,000 ⓘ

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