Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Integrated circuit configuration for testing transistors, and a semiconductor wafer having such a circuit configuration

Integrated circuit configuration for testing transistors, and a semiconductor wafer having such a circuit configuration

US Patent 6529031 · Granted Mar 4, 2003

Estimated economic value: $62,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Semiconductor chip with metallization levels, and a method for formation in inte2008
Semiconductor wafer with test structure2008
Integrated semiconductor memory2007
Integrated circuit for regulating a voltage generator2007
Semiconductor product having a semiconductor substrate and a test structure and 2007
Device architecture and process for improved vertical memory arrays2005
Test structure for improved vertical memory arrays2005
Test structure for determining a short circuit between trench capacitors in a me2005
Test structure for determining a region of a deep trench outdiffusion in a memor2005
Test structure for measuring a junction resistance in a DRAM memory cell array2005
Test structure for determining a doping region of an electrode connection betwee2005
Transistor array and semiconductor memory configuration fabricated with the tran2005