{"@context": "https://schema.org", "@type": "BreadcrumbList", "itemListElement": [{"@type": "ListItem", "position": 1, "name": "Home", "item": "https://www.patentleaderboard.com/"}, {"@type": "ListItem", "position": 2, "name": "Method and structure for improving hot carrier immunity for devices with very shallow junctions", "item": "https://www.patentleaderboard.com/patent/6512273"}]}
Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method and structure for improving hot carrier immunity for devices with very shallow junctions

Method and structure for improving hot carrier immunity for devices with very shallow junctions

US Patent 6512273 · Granted Jan 28, 2003

Estimated economic value: $2,528,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Negative capacitance matching in gate electrode structures2019
Negative capacitance matching in gate electrode structures2018
Fin-FET resonant body transistor2018
Methods to utilize piezoelectric materials as gate dielectric in high frequency 2018
Fin-FET resonant body transistor2018
III-V NFETs including channel barrier layers to reduce band-to-band leakage curr2017
Methods to utilize piezoelectric materials as gate dielectric in high frequency 2017
MEMs-based resonant FinFET2017
FinFET device with a graphene gate electrode and methods of forming same2014
High-voltage transistor device2014
Lateral high-voltage transistor and associated method for manufacturing2014
Methods and systems for memory devices with asymmetric switching characteristics2014