Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Variable read/write margin high-performance soft-error tolerant SRAM bit cell

Variable read/write margin high-performance soft-error tolerant SRAM bit cell

US Patent 6510076 · Granted Jan 21, 2003

Estimated economic value: $11,607,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Integrated circuit with cells having metal layer configured based on directions 2021
Multi supply cell arrays for low power designs2016
Method and apparatus for enhanced static IR drop analysis2014
Method and device for determining a duty cycle offset2009
Texture engine memory access synchronizer2007
Texture engine memory access synchronizer2004
Method and apparatus for improving stuck-at fault detection in large scale integ2001
Tristatable output driver for use with 3.3 or 5 volt CMOS logic1998
Built-in test scheme for a jitter tolerance test of a clock and data recovery un1998