Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Efficient metric memory configuration for a Viterbi decoder

Efficient metric memory configuration for a Viterbi decoder

US Patent 6438181 · Granted Aug 20, 2002

Estimated economic value: $1,097,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Method for transmitting an FSOC supervisor channel2021
Method for alignment of phase-sensitive tracking systems using variable delay of2021
Method for transmitting an FSOC supervisor channel2020
Method for alignment of phase-sensitive tracking systems using variable delay of2019
Method for transmitting an FSOC supervisor channel2019
Method and apparatus for time tracking a signal using hardware and software2003
Efficient apparatus and method for generating a trellis code from a shared state2003
Efficient apparatus and method for generating a trellis code from a shared state2003
Method for determining frame rate of a data frame in a communication system by u2003
Method and system of initializing state metrics for traffic, paging, and sync ch2003
Method and system of initializing state metrics for traffic, paging, and sync ch2003
Device and method for generating clock signals from a single reference frequency2002