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Home › Method and apparatus for elimination of parasitic bipolar action in complementary oxide semiconductor (CMOS) silicon on insulator (SOI) circuits

Method and apparatus for elimination of parasitic bipolar action in complementary oxide semiconductor (CMOS) silicon on insulator (SOI) circuits

US Patent 6365934 · Granted Apr 2, 2002

Estimated economic value: $31,515,000 ⓘ

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