{"@context": "https://schema.org", "@type": "BreadcrumbList", "itemListElement": [{"@type": "ListItem", "position": 1, "name": "Home", "item": "https://www.patentleaderboard.com/"}, {"@type": "ListItem", "position": 2, "name": "ATM node having local error correcting procedures", "item": "https://www.patentleaderboard.com/patent/6341132"}]}
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ATM node having local error correcting procedures

US Patent 6341132 · Granted Jan 22, 2002

Estimated economic value: $1,088,462,000 ⓘ

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