Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Timing-insensitive glitch-free logic system and method

Timing-insensitive glitch-free logic system and method

US Patent 6321366 · Granted Nov 20, 2001

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Porous compositions and related methods2022
Systems and methods for handling DPI messages outgoing from an emulator system2022
Common shared memory in a verification system2015
Common shared memory in a verification system2015
Common shared memory in a verification system2015
Co-simulation methodology to address performance and runtime challenges of gate 2015
Method and apparatus for simulating a circuit using timing insensitive glitch-fr2012
Method and apparatus for simulating a circuit using timing insensitive glitch-fr2012
Method and apparatus for simulating a circuit using timing insensitive glitch-fr2012
Method and apparatus for processing assertions in assertion-based verification o2012
Method and apparatus for implementing a task-based interface in a logic verifica2012
Method and apparatus for implementing a task-based interface in a logic verifica2012