Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method and apparatus for maintaining cache coherency in a computer system having multiple processor buses

Method and apparatus for maintaining cache coherency in a computer system having multiple processor buses

US Patent 6304945 · Granted Oct 16, 2001

Estimated economic value: $39,263,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Firmware update of an interconnect device2024
Providing power to a server2023
Firmware update of an interconnect device2022
Providing power to a server2021
Secure login information2020
Method for ethernet power savings on link aggregated groups2014
Network booting a machine coupled to the network by a link aggregation group2014
Method and apparatus for optimizing performance in a multi-processing system2006
Progressive CPU sleep state duty cycle to limit peak power of multiple computers2005
Method and apparatus for supporting heterogeneous memory in computer systems2003
Method and apparatus for tooless mating of liquid cooled cold plate with tapered2002
Method and apparatus for supporting heterogeneous memory in computer systems2001