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Home › Method and apparatus for elimination of parasitic bipolar action in logic circuits including complementary oxide semiconductor (CMOS) silicon on insulator (SOI) elements

Method and apparatus for elimination of parasitic bipolar action in logic circuits including complementary oxide semiconductor (CMOS) silicon on insulator (SOI) elements

US Patent 6278157 · Granted Aug 21, 2001

Estimated economic value: $21,309,000 ⓘ

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