{"@context": "https://schema.org", "@type": "BreadcrumbList", "itemListElement": [{"@type": "ListItem", "position": 1, "name": "Home", "item": "https://www.patentleaderboard.com/"}, {"@type": "ListItem", "position": 2, "name": "Master/slave data bus employing undirectional address and data lines and request/acknowledge signaling", "item": "https://www.patentleaderboard.com/patent/6256693"}]}
Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Master/slave data bus employing undirectional address and data lines and request/acknowledge signaling

Master/slave data bus employing undirectional address and data lines and request/acknowledge signaling

US Patent 6256693 · Granted Jul 3, 2001

Estimated economic value: $4,252,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Slave processor to slave memory data transfer with master processor writing addr2002
Multicast direct memory access storing selected ones of data segments into a fir2002
No stall read access-method for hiding latency in processor memory accesses2001
Method for improving interrupt response time2001