Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Clocking technique for reducing sampling noise in an analog-to-digital converter

Clocking technique for reducing sampling noise in an analog-to-digital converter

US Patent 6232905 · Granted May 15, 2001

Estimated economic value: $19,016,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Method and apparatus for downconverting a plurality of frequency modulated signa2012
Dual antenna system having one phase lock loop2012
Dual antenna system having one phase lock loop2008
Dual antenna receiver2007
Direct down-conversion receiver with transconductance-capacitor filter and metho2006
Biased Darlington transistor pair, method, and system2006
Receiver and low power digital filter therefor2006
Loop filter with active capacitor and method for generating a reference2006
Sigma-delta conversion with analog, nonvolatile trimmed quantized feedback2005
Strobe through differential signaling2005
Apparatus and method for determining process width variations in integrated circ2004
Tunable filter with bypass2003