Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Digital signal processor configuration including multiplying units coupled to plural accumlators for enhanced parallel mac processing

Digital signal processor configuration including multiplying units coupled to plural accumlators for enhanced parallel mac processing

US Patent 6230180 · Granted May 8, 2001

Estimated economic value: $34,441,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

System and method for structuring a large scale object recognition engine to max2017
Methods for efficient classifier training for accurate object recognition in ima2014
Methods, systems, and computer program products for translating machine code ass2007
Apparatus and method for an improved performance VLIW processor2006
Area and power efficient VLIW processor with improved speed2006
Method for reducing power when fetching instructions in a processor and related 2004
System for efficient operation of a very long instruction word digital signal pr2004
Apparatus and method for issue grouping of instructions in a VLIW processor2004
Apparatus and method for issue grouping of instructions in a VLIW processor2002
Reconfigurable functional units for implementing a hybrid VLIW-SIMD programming 2002
Processor containing data path units with forwarding paths between two data path2001
Efficient context saving and restoring in a multi-tasking computing system envir2000