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Home › Method and apparatus for reducing the apparent read latency when connecting busses with fixed read replay timeouts to CPU'S with write-back caches

Method and apparatus for reducing the apparent read latency when connecting busses with fixed read replay timeouts to CPU'S with write-back caches

US Patent 6226703 · Granted May 1, 2001

Estimated economic value: $33,544,000 ⓘ

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