Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method of fabricating crack resistant inter-layer dielectric for a salicide process

Method of fabricating crack resistant inter-layer dielectric for a salicide process

US Patent 6225209 · Granted May 1, 2001

Estimated economic value: $1,830,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Integration of multiple transistors having fin and mesa structures2025
Housing structure manufacturing method and electronic device2024
Computer case2021
Heating stage and apparatus having the same2021
Oxide semiconductor device and method of manufacturing the same2021
Computer case2021
Lens2020
Heat-dissipating device for expansion card and expansion card assembly with heat2018
Capacitor and method for fabricating the same2018
Method for fabricating semiconductor memory device having integrated DOSRAM and 2018
Semiconductor device2018
Oxide semiconductor device and method of manufacturing the same2018