Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Multiplexed noisy-quiet power busing for improved area efficiencies and pause performance in DRAM memories

Multiplexed noisy-quiet power busing for improved area efficiencies and pause performance in DRAM memories

US Patent 6219294 · Granted Apr 17, 2001

Estimated economic value: $18,422,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Synchronous input buffer control using a ripple counter2024
Row clear features for memory devices and associated methods and systems2024
Voltage adjustment based on pending refresh operations2023
Row clear features for memory devices and associated methods and systems2022
Apparatuses and methods for address detection2022
Power amplifier having a spread of graded outputs2021
Peripheral logic circuits under DRAM memory arrays2021
Apparatuses and methods for address detection2020
Apparatuses and methods for timing domain crossing2019
Apparatuses including a memory array with separate global read and write lines a2018
Apparatuses and methods for timing domain crossing2018
Apparatuses and methods for timing domain crossing2017