Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method for forming graded LDD transistor using controlled polysilicon gate profile

Method for forming graded LDD transistor using controlled polysilicon gate profile

US Patent 6191044 · Granted Feb 20, 2001

Estimated economic value: $7,201,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Self aligned memory element and wordline2010
Image processing in integrated circuit technology development2009
Method and apparatus for correlating semiconductor process data with known prior2007
Predicting defect future effects in integrated circuit technology development to2007
Self aligned memory element and wordline2007
Test structure and method for failure analysis of small contacts in integrated c2006
Wafer level global bitmap characterization in integrated circuit technology deve2006
Characterizing distribution signatures in integrated circuit technology2006
Fabrication of dual work-function metal gate structure for complementary field e2006
Sidewall formation for high density polymer memory element array2006
Flash memory cell with UV protective layer2006
Memory element formation with photosensitive polymer dielectric2005