Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method and apparatus for balancing load vs. store access to a primary data cache

Method and apparatus for balancing load vs. store access to a primary data cache

US Patent 6163821 · Granted Dec 19, 2000

Estimated economic value: $62,349,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Processor data cache with shared mid-level cache and low-level cache2025
Secure low-latency chip-to-chip communication2024
Low latency inter-chip communication mechanism in a multi-chip processing system2024
Methods and systems for distributing memory requests2024
Method and apparatus for managing global chip power on a multicore system on chi2023
Limiting backpressure with bad actors2023
Low latency inter-chip communication mechanism in a multi-chip processing system2023
Methods and systems for distributing memory requests2023
Methods and systems for distributing memory requests2021
Low latency inter-chip communication mechanism in multi-chip processing system2021
Shared mid-level data cache2021
Secure in-line received network packet processing2021