Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method of fabricating a MOS transistor with a raised source/drain extension

Method of fabricating a MOS transistor with a raised source/drain extension

US Patent 6121100 · Granted Sep 19, 2000

Estimated economic value: $252,989,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Double-sided integrated circuit transistor structures with depopulated bottom ch2025
Epitaxial source/drain back-side device contact structures with wrap around meta2025
Package architecture of photonic system with vertically stacked dies having plan2025
Gate-all-around integrated circuit structures having necked feature2025
Gate aligned fin cut for advanced integrated circuit structure fabrication2025
Integrated circuit structures having dielectric anchor void2025
Integrated circuit structures having differentiated channel sizing2025
Integrated circuit structures with backside self-aligned penetrating conductive 2025
Angled gate or diffusion plugs2025
SRAM with channel count contrast for greater read stability2025
Gate-all-around integrated circuit structures having underlying dopant-diffusion2025
Source or drain structures with relatively high germanium content2025