Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method and device for suppressing parasitic effects in a junction-isolation integrated circuit

Method and device for suppressing parasitic effects in a junction-isolation integrated circuit

US Patent 6060758 · Granted May 9, 2000

Estimated economic value: $49,402,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Duty cycle calibration circuit, corresponding transmitter, communication system 2025
Threshold voltage generator circuit and corresponding receiver device2025
Multi-environment flexible vehicle2023
Detection circuit, corresponding device and method2022
Electronic converter and method of operating an electronic converter2020
MEMS device with piezoelectric actuation, a projective MEMS system including the2020
MEMS device with piezoelectric actuation, a projective MEMS system including the2019
Programmable-gain amplifier, corresponding device and method2017
Package, made of building material, for a parameter monitoring device, within a 2017
Hall-effect-based magnetic field sensor having an improved output bandwidth2017
Magnetic inertial sensor and method for operating the same2017
Energy harvesting system with selectively activatable harvesting interface, and 2016