Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Circuit and method for generating clock signals with an incrementally reduced effective frequency

Circuit and method for generating clock signals with an incrementally reduced effective frequency

US Patent 6043692 · Granted Mar 28, 2000

Estimated economic value: $131,220,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

FPGA customizable to accept selected macros2002
Methods to securely configure an FPGA to accept selected macros2002
Method for configuring circuits over a data communications link2001
FPGA customizable to accept selected macros2001
Memory map computer control system for programmable ICS2000
System and method for controlled performance degradation in electronic circuits2000
Method for configuring circuits over a data communications link2000
Logic cell and routing architecture in a field programmable gate array1997