Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Multiple level cache control system with address and data pipelines

Multiple level cache control system with address and data pipelines

US Patent 6021471 · Granted Feb 1, 2000

Estimated economic value: $7,629,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Ring network element and the ring network architectures it enables2012
Any size and location of concatenated packet data across SONET frames in a SONET2008
Method and apparatus for processing channelized and unchannelized data within a 2008
Onboard RAM based FIFO with pointers to buffer overhead bytes of synchronous pay2007
Any size and location of concatenated packet data across SONET frames in a SONET2007
Method and apparatus for variable rate pipes2007
Ring network element and the ring network architectures it enables2007
Method and apparatus for disabling an interface between network element data pro2006
Protection mechanism for an optical ring2006
Any size and location of concatenated packet data across SONET frames in a SONET2006
Method and apparatus for switching data of different protocols2006
Method and apparatus for a hybrid variable rate pipe2005