Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Computer-system processor-to-memory-bus interface having repeating-test-event generation hardware

Computer-system processor-to-memory-bus interface having repeating-test-event generation hardware

US Patent 5958072 · Granted Sep 28, 1999

Estimated economic value: $45,902,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Method for allowing distributed high performance coherent memory with full error2009
Pass through debug port on a high speed asynchronous link2008
Display rotation using a small line buffer and optimized memory access2007
System and method for multi processor memory testing2006
Technique for testing processor interrupt logic2006
System and method for allowing non-trusted processors to interrupt a processor s2005
Method and apparatus for preventing underflow and overflow across an asynchronou2004
Circuit for allowing data return in dual-data formats2004
Method and apparatus for causing computer system interconnection to be in the sa2004
Method for triggering an asynchronous event by creating a lowest common denomina2004
Apparatus and method for detecting, diagnosing, and handling deadlock errors2003
System and method to protect vital memory space from non-malicious writes in a m2003